The elementary cell for such circuits is the adding cell or adder. In "Principles of CMOS VLSI Design" by N. H. E. Weste and Kamran Eshraghian published by Addison-Wesley Publishing Company, pp. 317-319, a full one-bit adder is described having three inputs: i.e. two operand inputs and one carry-in input. FIG. 1 shows such an adder. The adder has a first bit input (Ai), a second bit input (Bi) and a carry-in input (Ri-1 S). The adder produces a result signal (Si) and a carry-out signal (Ri S) using four inverting gates I1, I2, . . . , two exclusive-OR gates XOR1 and XOR2, and four transmission gates C1, C2, . . . . Each inverting gate I changes the logic state of the signal applied to its input. The exclusive-OR gate XOR1 calculates the two input bit exclusive-OR signal (Ai.sym.Bi) and the exclusive-OR gate XOR2 calculates the complemented two input bit exclusive-OR signal (Ai.sym.Bi). The transmission gates C1 and C2 calculate the carry-out signal (Ri S) and the transmission gates C3 and C4 calculate the result signal (Si). The various gates are constituted by one or more pairs of transistors T made of complementary MOS technology, i.e. having opposite polarities. The transistors are connected depending on the logical property of the gate in which they are included. As a result the adder comprises 24 transistors.
This adder is unsatisfactory in that it includes a large number of transistors.
The object of the present invention is to reduce the number of transistors in a full adder. To this end, it provides an adding cell which uses only 15 transistors in its most stripped-down version.